On Nanotechnology’s Fundamental Scaling Limits: A Study On The Impact Of Robustness To Delay Uncertainty On A Design’s Performance And Area

Nanoelectronic devices and interconnects will most likely exhibit substantial performance variability. Delivering high performance under such uncertainty conditions will require implementing more complex control and communication mechanisms between system components, in comparison to those used state of the art synchronous design. A key issue becomes thus to assess how the increased densities afforded by nanotechnologies will be countered by design overheads associated with achieving designs that are robust to performance variability. Towards this end, we consider two representative asynchronous design styles, one using asynchronous single rail channels (more suitable for low to moderate delay variability conditions), and another using asynchronous dual rail channels (more suitable for high delay variability), and assess their relative merits, for representative benchmarks. The experimental results of our study clearly exhibit the very substantial overheads/costs that will necessarily be incurred to achieve high performance under substantial delay uncertainty conditions, suggesting that such uncertainty may indeed be one of the fundamental scaling limits of nanotechnologies.